This invention pertains to boundary scan cell circuits (BSCC) provided in a corresponding manner to I/O pins of an integrated circuit (IC), to boundary scan test circuits (BSTC) for use in checking an inter-IC wiring subjected to testing for connection failures, and to a boundary scan testing.
Boundary scan testing has been developed as an attractive solution to problems accompanied with in-board wiring test techniques for checking, for example, printed circuit boards for the presence or absence of connection faulty. The accessing method as to boundary scan testing is standardized by IEEE1149.1. By referring to FIGS. 13-16, a BSCC structure conforming to IEEE1149.1 as well as a boundary scan test circuit structure for use in checking wire interconnection condition between on-board components by the use of an IEEE1149.1 BSCC is described.
FIG. 13 illustrates the organization of a boundary scan test circuit 200 employing a plurality of BSCCs. Provided on a printed circuit board are a plurality of ICs 210, 220, 230, and so on. The IC 210 (220, 230) comprises the following main components: a TAP controller (not shown in the figure) for controlling the operation of BSTC in-IC units; a plurality of connection terminals 215 (225, 235) for signal transfer between the ICs; and a plurality of BSCCs 100 (100, 100) the number of which is equal to the number of the connection terminals 215 (225, 235), each BSCC 100 being provided between an internal logic 212 (222, 232) and each connection terminal 215. In FIG. 13, connected between each connection terminal 215 and each connection terminal 225, between each connection terminal 225 and each connection terminal 235, between each connection terminal 235 and each connection terminal 215 are target wires W.sub.ts which are signal lines subjected to testing. As a result of such arrangement, a particular wire W.sub.ts is checked for connection failures such as disconnection according to the signal state. All of the BSCCs 100 are connected with one another in series, and a scan path 150 is provided in such a way that a scan signal S.sub.scan can pass through every IC. When checking W.sub.ts for stuck-at faults, a test logic signal (i.e. test data) is applied to a BSCC 100 through the scan path 150, which is hereinafter termed as "scan-in", whereas a logic signal (i.e. a result of the test) that has entered a BSCC 100 over W.sub.ts is output through the scan path 150, which is hereinafter termed as "scan-out". FIG. 13 shows various terminals. TDO is a scan signal output terminal at which S.sub.scan signal from the IC 220 is output. TDI is a scan signal input terminal at which S.sub.scan signal is input. TCK is a clock signal input terminal at which a clock signal is input. TMS is a test mode selection signal input terminal at which a test mode selection signal is input. TRST is a reset signal input terminal at which a reset signal is input.
By making reference to FIG. 14, the organization of the conventional BSCC 100 conforming to IEEE1149.1 is described. As shown in FIG. 14, the BSCC 100 comprises a first selector 102 which accepts two different input signals thereby outputting one of these two input signals according to a control signal S.sub.ca, a second selector 103 which also accepts two different input signals thereby outputting one of these two input signals according to a control signal S.sub.cc, a first flip-flop 104 which operates in synchronism with a clock signal S.sub.cd, a second flip-flop 105 which also operates in synchronism with a clock signal S.sub.ce, and a buffer 107 which gives a logic "1" output or a logic "0" output, these two logic outputs having the same drive power. In addition to the foregoing components, the BSCC 100 has a logic signal input terminal 101 at which a logic signal enters the BSCC 100, a scan signal input terminal 106 at which S.sub.scan scan signal from the scan path 150 enters the BSCC 100, control terminals 110a, 110c , 110d, and 110e at which S.sub.ca control signal. S.sub.cc control signal, S.sub.cd clock signal, and S.sub.ce clock signal are respectively input to the BSCC 100, a scan signal output terminal 108 at which S.sub.scan scan signal is sent out down to the scan path 150, and a logic signal output terminal 109 at which a logic signal leaves the BSCC 100.
Of the two input signals to the first selector 102, one is a logic signal S.sub.lg from the logic signal input terminal 101 and the other is S.sub.scan signal from the scan signal scan input terminal 106. The first selector 102 gives its output to the first flip-flop 104. The first flip-flop 104 outputs to the second flip-flop 105. Of the two input signals to the second selector 103, one is S.sub.lg logic signal from the logic signal input terminal 101 and the other is the output of the second flip-flop 105. The second selector 103 gives its output to the buffer 107. The output of the buffer 107 is applied to the logic signal output terminal 109 at which it leaves the BSCC 100. The BSCC 100 may be provided on the input side or on the output side, however, the basic structure of the BSCC 100 will not change with respect to the layout location.
FIG. 15 shows an interconnection of a BSCC 100 of the IC 210 serving as an output BSCC with a BSCC 100 of the IC 220 serving as an input BSCC. In the IC 210, the logic signal input terminal 101 is connected to the internal logic 212 and the logic signal output terminal 109 is connected to the connection terminal 215 which is an output pin. In the IC 220, on the other hand, the logic signal input terminal 101 is connected to the connection terminal 225 that is an input pin and the logic signal output terminal 109 is connected to the internal logic 222.
If the first selector 102 of the BSCC 100 in the first IC 210 selects S.sub.scan scan signal according to the logic state of S.sub.ca control signal, this serially connects all the first flip-flops 104 within the first IC 210. S.sub.scan scan signal is output at the TDO terminal. Thereafter, S.sub.scan scan signal is sequentially applied to the IC 210, to the IC 220, and so on through their respective scan signal input terminals 106, and is output at their respective scan output terminals 108.
How the boundary scan test circuit 200 checks W.sub.ts for stuck-at "0" faults is explained.
A logic value of "1" is pre-stored, by issuing a SAMPLE/PRELOAD instruction, in the second flip-flop 105 of the BSCC 100 of the IC 210. Then, an EXTEST instruction is executed. This changes the logic value of S.sub.cc control signal to a logic "1" and a "1" is output at the connection terminal 215. FIG. 16 is the state transition diagram of a TAP controller to IEEE1149.1. When the TAP controller is in the "Capture-DR" state, S.sub.ca control signal comes to have a logic value of "0", and a logic value (i.e. a result of the testing), passing through W.sub.ts, is latched by the first flip-flop 104 of the input BSCC 100 of the IC 220. Next, when the TAP controller is in the "Shift-DR" state, S.sub.ca control signal comes to have a logic value of "1" and the scan path 150 enters the communication state while at the same time that logic value latched by the first flip-flop 104 is scanned-out. Of all the serial data scanned-out, a logic value string (i.e. a result of the testing) is checked against the input test data "1" so as to check W.sub.ts for the presence or absence of stuck-at "0" faults. For the case of checking W.sub.ts for stuck-at "1" faults, the output BSCC 100 outputs a logic value of "0" and the input BSCC 100 scans-out a test result to the scan path 150.
To sum up, if a logic value received by the input BSCC 100 through W.sub.ts matches one provided by the output BSCC 100, this indicates that the connection state of W.sub.ts is good. If the input BSCC 100 receives a logic value of "0" although the output BSCC 100 provides a logic value of "1", this is indicative of the occurrence of stuck-at "0" faults. Conversely, if output of a logic value of "0" results in input of logic value of "1", this is indicative of the occurrence of stuck-at "1" faults.
In general, two different test data items are required to perform the above-described stuck-at "0"/"1" fault testing, namely one formed by a particular logic value string and the other formed by inverting that particular logic value string. More specifically, in the case of making an output BSCC provide test data items of "0", "0", "0", "1", . . . onto a wire subjected to testing, it is necessary to apply test data items of "1", "1", "1", "0", . . . to that output BSCC. Meanwhile, upon receiving a logic signal over the wire, an input BSCC must supply both a test result against the non-inverted test data and another test result against the inverted test data onto a scan path. Accordingly, if wires subjected to testing total to N, the number of shift operation cycles is 4N cycles when performing stuck-at "0"/"1" fault testing. This produces a problem that as the I/O pin count (i.e. the wire count) increases testing time dramatically increases.
U.S. Pat. No. 5,084,874 shows a BSCC that comprises an input logic, a multiplexer capable of selecting between signals, a first and a second flip-flop for latching a signal from the multiplexer for a predetermined length of time, wherein the multiplexer and these two flip-flops are connected in series and the inverted output of the second flip-flop is fed back to the multiplexer. In such a prior art BSCC, however, since signals to a logic signal output terminal are always provided via the multiplexer and two flip-flops, this requires capture cycles for outputting the inversion logic to a logic signal output terminal. For this reason, testing circuitry becomes complicated since the way of controlling multiplexers is different between an input BSCC and an output BSCC. Therefore, the prior art techniques have difficulties in reducing testing time.